View M466F0804DT1-L_2390785.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dram module M466F0804DT1-L rev. 0.1 oct. 2000 M466F0804DT1-L edo mode 8m x 64 dram sodimm using 4mx16, 4k refresh 3.3v, low power/self-refresh the samsung M466F0804DT1-L is a 8mx64bits dynamic ram high density memory module. the samsung M466F0804DT1-L consists of eight cmos 4mx16bits drams in tsop 400mil packages and a 2k eeprom in 8-pin tssop package mounted on a 144-pin glass-epoxy sub- strate. a 0.1uf decoupling capacitor is mounted on the printed circuit board for each dram. the M466F0804DT1-L is a small out-line dual in-line memory module and is intended for mounting into 144 pin edge connector sockets. ? part identification - M466F0804DT1-L(4096 cycles/128ms, tsop, l-ver) ? extended data out mode operation ? new jedec standard proposal with eeprom ? serial presense detect with eeprom ? cas -before- ras refresh capability ? self -refresh capability ? ras -only and hidden refresh capability ? lvttl compatible inputs and outputs ? single +3.3v 0.3v power supply ? pcb : height(1000mil), double sided component general description features performance range speed t rac t cac t rc t hpc -l50 50ns 13ns 84ns 20ns -l60 60ns 15ns 104ns 25ns pin configurations pin front pin back pin front pin back pin front pin back 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 v ss dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 v ss cas0 cas1 v cc a0 a1 a2 v ss dq8 dq9 dq10 dq11 v cc dq12 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 v ss dq32 dq33 dq34 dq35 v cc dq36 dq37 dq38 dq39 v ss cas4 cas5 v cc a3 a4 a5 v ss dq40 dq41 dq42 dq43 v cc dq44 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 dq13 dq14 dq15 v ss rsvd rsvd rfu v cc rfu w ras0 ras1 oe v ss rsvd rsvd v cc dq16 dq17 dq18 dq19 v ss dq20 dq21 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 dq45 dq46 dq47 v ss rsvd rsvd rfu v cc rfu rfu rfu rfu rfu v ss rsvd rsvd v cc dq48 dq49 dq50 dq51 v ss dq52 dq53 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 dq22 dq23 v cc a6 a8 v ss a9 a10 v cc cas2 cas3 v ss dq24 dq25 dq26 dq27 v cc dq28 dq29 dq30 dq31 v ss sda v cc 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 dq54 dq55 v cc a7 a11 v ss nc nc v cc cas6 cas7 vss dq56 dq57 dq58 dq59 v cc dq60 dq61 dq62 dq63 vss scl v cc pin names pin name function a0 to address inputs dq0 - dq63 data in/out w read/write enable oe output enable ras0 , ras1 row address strobe cas0 - cas7 column address strobe v cc power(+3.3v) v ss ground nc no connection sda serial address / data i/o scl serial clock rsvd reserved use rfu reserved for future use
dram module M466F0804DT1-L rev. 0.1 oct. 2000 cas4 cas5 cas6 cas7 cas0 cas1 cas2 cas3 functional block diagram u0 v cc vss 0.1uf capacitor for each dram to all drams u1 ras1 w oe a0-a11 serial pd sda scl vss a1 a2 a0 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u4 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u5 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ras0 u2 u6 u7 u3 dq16~31 dq48~63 dq0~15 dq32~47 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas ucas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas ucas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas ucas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas ucas
dram module M466F0804DT1-L rev. 0.1 oct. 2000 * note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one edo mode cycle time, t hpc . absolute maximum ratings * * permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for in tended periods may affect device reliability. item symbol rating unit voltage on any pin relative v ss voltage on v cc supply relative to v ss storage temperature power dissipation short circuit output current v in , v out v cc t stg p d i os -0.5 to +4.6 -0.5 to +4.6 -55 to +125 8 50 v v c w ma recommended operating conditions (voltage referenced to v ss , t a = 0 to 70 c) *1 : v cc +1.3v at pulse width 15ns, which is measured at v cc . *2 : -1.3v at pulse width 15ns, which is measured at v ss . item symbol min typ max unit supply voltage ground input high voltage input low voltage v cc v ss v ih v il 3.0 0 2.0 -0.3 *2 3.3 0 - - 3.6 0 v cc +0.3 *1 0.8 v v v v dc and operating characteristics (recommended operating conditions unless otherwise noted) i cc1 i cc2 i cc3 i cc4 i cc5 i cc6 i cc7 i ccs i (il) i (ol) v oh v ol symbol speed M466F0804DT1-L unit min max i cc1 -50 -60 - - 484 444 ma ma i cc2 don t care - 8 ma i cc3 -50 -60 - - 484 444 ma ma i cc4 -50 -60 - - 364 324 ma ma i cc5 don t care - 1.6 ma i cc6 -50 -60 - - 484 444 ma ma i cc7 i ccs don t care - - 2.8 2.8 ma ma i i(l) i o(l) don t care -10 -10 10 10 ua ua v oh v ol don t care 2.4 - - 0.4 v v : operating current * ( ras , cas , address cycling @t rc =min) : standby current ( ras = cas = w =v ih ) : ras only refresh current * ( cas =v ih , ras cycling @ t rc =min) : extended data out mode current * ( ras =v il , cas cycling : t hpc =min) : standby current ( ras = cas = w =v cc -0.2v) : cas -before- ras refresh current * ( ras and cas cycling @ t rc =min) : battery back-up current. average power supply, battery back-up mode. input high voltage(v ih )=v cc -0.2v, input low voltage(v il )=0.2v, ucas , lcas =0.2v, dq=don t care, t rc =31.25us, t ras = t ras min~300ns : self refresh current, ras = ucas = lcas =v il , w = oe =a0~a11=v cc -0.2v or 0.2v, dq~dq63=v cc -0.2v or open : input leakage current (any input 0 v in vcc+0.3v, all other pins not under test=0 v) : output leakage current(data out is disabled, 0v v out v cc ) : output high voltage level (i oh = -2ma) : output low voltage level (i ol = 2ma)
dram module M466F0804DT1-L rev. 0.1 oct. 2000 capacitance (t a = 25 c, v cc =3.3v, f = 1mhz) item symbol min max unit input capacitance[a0-a11] input capacitance[ w , oe ] input capacitance[ ras0 , ras1 ] input capacitance[ cas0 - cas7 ] input/output capacitance[dq0 - 63] c in1 c in2 c in3 c in4 c dq - - - - - 50 66 38 24 24 pf pf pf pf pf ac characteristics (0 c t a 70 c, v cc =3.3v 0.3v. see notes 1,2.) test condition : v ih /v il =2.2/0.7v, v oh /v ol =2.0/0.8v, output loading cl=100pf parameter symbol -50 -60 unit note min max min max random read or write cycle time t rc 84 104 ns read-modify-write cycle time t rwc 128 153 ns access time from ras t rac 50 60 ns 3,4,9 access time from cas t cac 13 15 ns 3,4,5 access time from column address t aa 25 30 ns 3,9 cas to output in low-z t clz 3 3 ns 3 oe to output in low-z t olz 3 3 ns 3 output buffer turn-off delay from cas t cez 3 13 3 13 ns 3,11 transition time(rise and fall) t t 1 50 1 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 8 10 ns cas hold time t csh 38 40 ns cas pulse width t cas 8 10k 10 10k ns ras to cas delay time t rcd 17 37 20 45 ns 4 ras to column address delay time t rad 12 25 15 30 ns 9 cas to ras precharge time t crp 5 5 ns row address set-up time t asr 0 0 ns row address hold time t rah 7 10 ns column address set-up time t asc 0 0 ns 12 column address hold time t cah 7 10 ns 12 column address to ras lead time t ral 25 30 ns read command set-up time t rcs 0 0 ns read command hold referenced to cas t rch 0 0 ns 7 read command hold referenced to ras t rrh 0 0 ns 7 write command set-up time t wcs 0 0 ns 6 write command hold time t wch 7 10 ns 6 write command pulse width t wp 7 10 ns write command to ras lead time t rwl 8 10 ns write command to cas lead time t cwl 7 10 ns 15 data set-up time t ds 0 0 ns 8,18 data hold time t dh 7 10 ns 8,18 refresh period t ref 128 128 ms cas to w dealy time t cwd 33 38 ns 6,14 ras to w dealy time t rwd 70 84 ns 6
dram module M466F0804DT1-L rev. 0.1 oct. 2000 test condition : v ih /v il =2.2/0.7v, v oh /v ol =2.0/0.8v, output loading cl=100pf parameter symbol -50 -60 unit note min max min max column address to w delay time t awd 45 53 ns 6 cas precharge to w delay time t cpwd 47 58 ns 6 cas setup time ( cas -before- ras refresh) t csr 5 5 ns 16 cas hold time ( cas -before- ras refresh) t chr 10 10 ns 17 ras to cas precharge time t rpc 5 5 ns access time from cas precharge t cpa 28 35 ns 3 hyper page mode cycle time t hpc 20 25 ns 10 hyper page mode read-modify write cycle time t hprwc 67 73 ns 10 cas precharge time (hyper page cycle) t cp 7 10 ns 13 ras pulse width (hyper page cycle) t rasp 50 200k 60 200k ns ras hold time from cas precharge t rhcp 30 35 ns w to ras precharge time (c-b-r refresh) t wrp 10 10 ns w to ras hold time (c-b-r refresh) t wrh 10 10 ns oe access time t oea 13 15 ns 3 oe to data delay t oed 10 13 ns output buffer turn off delay time from oe t oez 3 13 3 13 ns oe command hold time t oeh 5 5 ns output data hold time t doh 5 5 ns output buffer turn off delay from ras t rez 3 13 3 15 ns 11 output buffer turn off delay from w t wez 3 13 3 15 ns w to data delay t wed 15 15 ns oe to cas hold time t och 5 5 ns cas hold time to oe t cho 5 5 ns oe precharge time t oep 5 5 ns w pulse width(hyper page cycle) t wpe 5 5 ns ras pulse width (c-b-r self refresh) t rass 100 100 us 19,20,21 ras precharge time (c-b-r self refresh) t rps 90 110 ns 19,20,21 cas hold time (c-b-r self refresh) t chs -50 -50 ns 19,20,21 ac characteristics (0 c t a 70 c, v cc =3.3v 0.3v. see notes 1,2.)
dram module M466F0804DT1-L rev. 0.1 oct. 2000 notes an initial pause of 200us is required after power-up followed by any 8 ras -only or cas -before- ras refresh cycles before proper device operation is achieved. input voltage levels are v ih /v il . v ih (min) and v il (max) are ref- erence levels for measuring timing of input signals. transi- tion times are measured between v ih (min) and v il (max) and are assumed to be 5ns for all inputs. measured with a load equivalent to 1 ttl loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). t wcs , t rwd , t cwd , t awd and t cpwd are non-restrictive operat- ing parameter. they are included in the data sheet as electri- cal characteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain high imped- ance for the duration of the cycle. if t rwd 3 t rwd (min), t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min). the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to the cas leading edge in early write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as reference point only. if t rad is greater than the specified t rad (max) limit access time is controlled by t aa . 1. 2. 3. 4. 5. 6. 7. 8. 9. t asc 3 6ns, assume tt=2.0ns if ras goes high before cas high going, the open circuit condition of the output is achieved by cas high going. if cas goes high before ras high going , the open circuit condition of the output is achieved by ras going. t asc is referenced to the earlier cas falling edge and t cah is referenced to the later cas falling edge. t cp is specified from the last cas rising edge in the previous cycle to the first cas falling edge in the next cycle. t cwd is referenced to the later cas falling edge at word read- modify-write cycle. t cwl is specified from w falling edge to the earlier cas rising edge. t csr is referenced to earlier cas falling edge to the ras fall- ing edge. t chr is referenced to the later cas rising from ras falling edge. t ds , t dh is specified by the earlier cas falling edge. if t rass 3 100us, then ras precharge time must use t rps instead of t rp . for ras -only refresh and burst cas -before- ras refresh mode, 4096 cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. for distributed cas -before- ras with 15.6us interval cas - before- ras should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specifi- cation. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.
dram module M466F0804DT1-L rev. 0.1 oct. 2000 ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t asr t rah t asc t cah t crp t aa t oea t clz t rac open t rch don t care undefined t rad t rrh data-out t rez t rcs read cycle t oez t cez t wez dq t olz t cac
dram module M466F0804DT1-L rev. 0.1 oct. 2000 t wcs note : d out = open write cycle ( early write ) ras v ih - v il - v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp don t care undefined t wch t wp cas t rwl t cwl t ds t dh data-in dq
dram module M466F0804DT1-L rev. 0.1 oct. 2000 note : d out = open write cycle ( oe controlled write ) ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t wp don t care undefined cas v ih - v il - t rwl t cwl t dh t oeh t oed data-in t ds
dram module M466F0804DT1-L rev. 0.1 oct. 2000 read - modify - write cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp valid t wp don t care t rwl t cwl t oez t oea t oed t awd t cwd t rwd data-out undefined valid data-in t rac t aa t cac t clz t ds t dh column address t olz
dram module M466F0804DT1-L rev. 0.1 oct. 2000 t doh hyper page read cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp t rcd t asr t crp don t care undefined v oh - v ol - dq t oep column address t cas t cas t cas t cas t cp t cp t cp t hpc t hpc t hpc t rhcp t csh t rad t rah t asc t cah t cah t cah t asc t cah t rcs t aa t rch t asc column address column addr valid data-out t oez t oea t oep t aa t cac t oea t aa t cpa t cac t cpa valid data-out valid data-out t oez t clz t rac t oea t olz t cac t rrh t cho t rez t oez t cac t och t cpa t cac valid data-out ? t asc t aa
dram module M466F0804DT1-L rev. 0.1 oct. 2000 ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr. t rasp t rp t rcd t asr t crp don t care hyper page write cycle ( early write ) undefined v ih - v il - dq t rhcp t rad t rah t cah t cah t asc t cah t asc valid data-in t ds ? column address column address t cas t cp t cas t cp t cas t rsh ? t csh t asc ? ? t wp t wcs t wch t wp t wcs t wch t wp t wcs t wch ? ? ? valid data-in valid data-in ? ? t dh t ds t dh t ds t dh t cwl t cwl t cwl t rwl note : d out = open t hpc t hpc
dram module M466F0804DT1-L rev. 0.1 oct. 2000 don t care hyper page read-modify-write cycle undefined ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - row addr t csh t rasp t rp t asr t rah t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t asc t cah t ral t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t rac t oea t clz t oez t cpwd t oed t asc t clz t oea t cac t aa t dh t oed t rwl t crp t ds t oez valid data-out valid data-in valid data-out valid data-in t ds dq t rsh t olz t olz t hprwc t cac t aa
dram module M466F0804DT1-L rev. 0.1 oct. 2000 hyper page read and write mixed cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp don t care undefined v i/oh - v i/ol - dq t wez t cp t cp t hpc t hpc t hpc t rad t rah t asc t cah t cah t cah t asc t cah t rch t rcs t rcs t rch t asc column address col. addr valid data-out t rez t aa t wcs valid data-out valid data-out valid data-in t rac col. addr t cas t asr t cas t cas t cas t asc t cp t rch t wch t wpe t clz t cpa t wed t aa t wez t ds t dh t cac t oea read( t cac ) read( t cpa ) write read( t aa )
dram module M466F0804DT1-L rev. 0.1 oct. 2000 don t care ras - only refresh cycle* note : w , oe , d in = don t care undefined d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t rc t rp t asr t crp t ras t rah t rpc t crp open cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rc t rp t ras t rpc t cp t rpc t csr t chr t cez v oh - v ol - dq t wrp t wrh w v ih - v il - t rp * in ras -only refresh cycle of 64mb a-dile & b-die, when cas signal transits from low to high, the valid data may be cut off.
dram module M466F0804DT1-L rev. 0.1 oct. 2000 hidden refresh cycle ( read ) t oez data-out t rp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t chr t rcd t rsh t rad t asr t rah t asc t crp don t care undefined v oh - v ol - dq t wrh t rrh column address t oea t ras t rc t cah t rcs t aa t rac t clz t cac t cez open t rp t wez t rez t olz t wrp
dram module M466F0804DT1-L rev. 0.1 oct. 2000 t crp t wcs t rp ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t rad t asr t rah t asc don t care hidden refresh cycle ( write ) undefined cas v ih - v il - v ih - v il - dq t rsh t rcd t wrh column address t ras t rc t chr t cah t wrp t ds note : d out = open t wp t wch data-in t dh t rp
dram module M466F0804DT1-L rev. 0.1 oct. 2000 cas -before- ras refresh counter test cycle ras v ih - v il - cas v ih - v il - a v ih - v il - column address t ras t rsh t chr t ral t csr t cpt t rp t cas t asc t cah read cycle v oh - v ol - data-out dq t rez t clz write cycle v ih - v il - data-in dq t dh t ds w v ih - v il - t wp t cwd t cwl t rwl read-modify-write t awd v ih - v il - oe t oea t aa t cac t ds t dh valid data-out v i/oh - v i/ol - dq don t care undefined v ih - v il - oe t oea t oez oe v ih - v il - t rcs t clz t oez t oed t wrp t wrh t rrh t rch t rcs t cac t aa v ih - v il - w t wrp t wrh t wcs t wch t cwl v ih - v il - w t wp t rwl t wrp t wrh valid data-in note : this timing diagram is applied to all devices besides 64m dram based modules. t cez t wez
dram module M466F0804DT1-L rev. 0.1 oct. 2000 open cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rps t rass t rpc t cp t rpc t csr t cez v oh - v ol - dq t rp don t care undefined t chs t wrp t wrh w v ih - v il - open test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rp t rc t rpc t cp t rpc t csr t cez v oh - v ol - dq t wts t wth w v ih - v il - t chr t rp t ras
dram module M466F0804DT1-L rev. 0.1 oct. 2000 package dimensions 2.66(67.60) 2.50(63.60) 2- f 0.07 units : inches (millimeters) 0.024 0.001 0.03 typ 0.150max (3.81max ) 0.04 0.0039 tolerances : .005(.13) unless otherwise specified the used device is 4mx16 dram with edo mode, tsop ii dram part no. : k4e641612d-t (1.80) 0.13(3.30) (1.00 0.10) 2-r 0.078 min (2.00 min) 0.18 (4.60) 0.083 (2.10) 0.10 (2.50) 0.91(23.20) 1.29(32.80) 0 . 2 4 ( 6 . 0 ) 0.16 0.039 (4.00 0.1) 0 . 7 9 ( 2 0 . 0 0 ) 1 . 0 1 ( 2 5 . 6 5 4 ) z y 1.15 (3.70) 0.162 min (4.11 min) 0.06 0.0039 (1.50 0.1) detail z (0.80 typ) (0.60 0.05) 0 . 1 0 m i n ( 2 . 2 5 m i n ) detail y 0.160 0.0039 (4.00 0.1) ( back view ) ( front view ) 0.008 0.006 (0.200 0.150 )

▲Up To Search▲

Price & Availability of M466F0804DT1-L

	To Download M466F0804DT1-L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .